This invention relates to printed circuit boards for electronic device packages such as ball grid array packages or organic chip carrier packages.
Printed circuit or wiring boards are currently used in electronic device packages, multichip modules, or organic chip carrier packages wherein the electronic device, such as integrated circuit chip(s) or memory chip(s), are directly attached to the printed circuit board. Such an electronic device package is necessary due to the large number of input/output contacts of the electronic device. The electronic device package is typically used to electrically couple the electronic device to an external printed circuit board. An example of such an electronic device package is a ball grid array package or organic chip carrier package such as found in U.S. Pat. No. 5,355,283. Previously, such packages were based on ceramic or multi-layer ceramic packages. For electrical performance, cost, and other reasons, the packages are being converted to printed circuit board based packages.
FIG. 1 is a cross-sectional view of a prior art ball grid array package 10. An integrated circuit chip or electronic device 12 is attached to a prepreg-based substrate 14 comprising glass cloth or fabrics impregnated with epoxy resin, sometimes referred to as sticker sheets or prepreg. Electrically conductive bond wires 16 make electrical connection between selected one of contacts (not shown) formed on the electronic device 12 and electrically conductive circuitry 18 formed on top surface 20 of the substrate 14. Encapsulant 22 is formed on top surface 20 of substrate 14 to cover electronic device 12, bond wires 16, and a portion of circuitry 18. Circuitry 18 extends beyond encapsulant 22 to through holes 24 that are formed through substrate 14 to bottom surface 26 of substrate 14. Through holes 24 are plated with electrically conductive material and thus are often referred to as plated through holes. Electrically conductive traces 28 formed on the bottom surface 26 of substrate 14 extend from through holes 24 to pads 30 on which solder balls 32 are formed. In the conventional ball grid array 10, electrical connection between circuitry 18 on top surface 20 and traces 28 on bottom surface 26 of substrate 14 is made by through holes 24. Although not shown, substrate 14 may also include one or more internal circuit planes embedded therein. These planes may serve as signal, power, voltage, or ground planes and are usually incorporated in pairs. Such subcomposites are often called cores.
It is to be noted that substrate 14, circuitry 18, plated through holes 24, traces 28, and pads 30 form a printed circuit board (PCB) 33. Printed circuit boards are sometimes referred to as printed wiring boards (PWBs). Electronic device packages using printed circuit boards having glass-based prepreg substrates are prone to failures caused by shorts between circuitry 18 located on top surface 20, traces 28 located on bottom surface 26, or between power cores and the electrical traces 28 or circuitry 18 or between two power cores (not shown in FIG. 1) or between a power core and a plated through hole or between a plated through hole and traces 28 or circuitry 18.
In particular, shorts due to electrochemical migration are known to occur and are described as cathodic anodic filaments (CAF). The formation of CAFs is described in detail in B. Rudra, M. J. Li, M. Pecht, and D. Tennings, xe2x80x9cElectrochemical Migration in Multichip Modules,xe2x80x9d Circuit World, Vol. 22, No. 1, pp. 67-70 (1995), and in W. J. Ready, S. R. Stock, G. B. Freeman, L. L. Dollar, and L. J. Turbini, xe2x80x9cMicrostructure of Conductive Anodic Filaments Formed During Accelerated Testing of Printed Wiring Boards,xe2x80x9d Circuit World, Vol. 21, No. 4, pp. 5-9 (1995). JEDEC module test requirements, such as a highly accelerated stress test (HAST) using 130xc2x0 C., 85% relative humidity, bias, 100 hours, and temperature humidity bias test (THB) using 85xc2x0 C., 85% relative humidity, bias, 1000 hours, are likely to develop such shorts in laminate chip carriers. These test conditions are orders of magnitude more severe than conventional IPC insulation resistance tests (50xc2x0 C., 80% relative humidity, bias, 300 hours). The IPC test requirements are fulfilled by these organic chip carrier packages easily.
Referring to FIG. 2, such shorting failures are illustrated wherein reference numerals which are like or similar to the reference numerals in FIG. 1 indicate like or similar parts. FIG. 2 illustrates a portion of a printed circuit board 33 for use in an electronic device package 10. Printed circuit board 33 includes power planes 34, 36 embedded within substrate 14. Substrate 14 includes sticker sheets containing glass fibers 38, 40, 42 as shown schematically. Conductive material in circuitry 18, plated through hole 24, or power planes 34, 36 migrate along the glass fibers contained within prepreg 38, 40, 42 to form conductive filaments 44, 46, 48 along the glass fibers. Filaments 44 create a conductive path or short between circuitry 18a and circuitry 18b. As spacing 50 between circuitry 18a and 18b decreases, the likelihood of such shorts increases. Filaments 46, in the sticker sheets on the inside of the core, create a short between power plane 34 and plated through hole 24 such as by bridging the clearance hole between the power plane 34 and plated through hole 24. Filaments 48 in the prepreg outside the core create a short between power plane 36 and plated through hole 24 such as by bridging the clearance hole between power plane 36 and plated through hole 24. It will be appreciated that other shorting conditions can be caused by other CAFs formed within substrate 14. What is needed is a printed circuit board design for use in an electronic device package which eliminates short failures caused by plating of conductive material or migration along glass fibers contained within the printed circuit board.
Accordingly, the present invention is directed to a printed circuit board for use in an electronic device package comprising a substrate layer comprising impregnated glass fibers; a non-conductive layer comprising a glass-free or non-continuous glass-fibers dielectric material laminated to the substrate layer and a electrically conductive circuitry comprising a conductive material formed on the non-conductive layer such that the non-conductive layer lies between the substrate layer and the conductive material to prevent shorts therebetween caused by migration of the conductive material along continuous glass fibers.
The present invention is also directed to an electronic device package comprising at least one substrate wherein the substrate comprises impregnated glass fibers; an electronic device coupled to the substrate; a non-conductive layer comprising a glass-free dielectric material laminated to each substrate and an electrically conductive circuitry comprising a conductive material formed on the nonconductive layers or the substrates such that each non-conductive layer lies between each substrate and conductive material to prevent shorts therebetween caused by electrochemical migration of the conductive material along the glass fibers.
The present invention is also directed to an electronic device package comprising at least one substrate wherein each substrate comprises impregnated glass fibers; at least one plated through hole extending through each substrate; at least one conductive power core; an electronic device coupled to at least one of the substrates and a non-conductive layer comprising a glass-free dielectric material positioned between each plated through hole and each power core to prevent a short therebetween caused by electrochemical migration of conductive material along the glass fibers.
The present invention is also directed to an electronic device package comprising a non-conductive substrate comprising a glass-free dielectric material; an electronic device coupled to the substrate and electrically conductive circuitry comprising a conductive material formed on the substrate wherein the electronic device is electrically coupled to the circuitry.
The primary advantage of the present invention is the elimination of CAF shorts in all printed circuit boards, including printed circuit boards used in electronic device packages.